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FEATURES Mixer -15 dBm 1 dB Compression Point -5 dBm IP3 24 dB Conversion Gain >500 MHz Input Bandwidth Logarithmic/Limiting Amplifier 80 dB RSSI Range 3 Phase Stability over 80 dB Range Low Power 21 mW at 3 V Power Consumption CMOS-Compatible Power-Down to 300 200 ns Enable/Disable Time APPLICATIONS PHS, GSM, TDMA, FM, or PM Receivers Battery-Powered Instrumentation Base Station RSSI Measurement
Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem AD608
The RF and LO bandwidths both exceed 500 MHz. In a typical IF application, the AD608 will accept the output of a 240 MHz SAW filter and downconvert it to a nominal 10.7 MHz IF with a conversion gain of 24 dB (ZIF = 165 ). The AD608's logarithmic/limiting amplifier section handles any IF from LF to as high as 30 MHz. The mixer is a doubly-balanced "Gilbert-Cell" type and operates linearly for RF inputs spanning -95 dBm to -15 dBm. It has a nominal -5 dBm third-order intercept. An onboard LO preamplifier requires only -16 dBm of LO drive. The mixer's current output drives a reverse-terminated, industry-standard 10.7 MHz 330 filter. The nominal logarithmic scaling is such that the output is +0.2 V for a sinusoidal input to the IF amplifier of -75 dBm and +1.8 V at an input of +5 dBm; over this range the logarithmic conformance is typically 1 dB. The logarithmic slope is proportional to the supply voltage. A feedback loop automatically nulls the input offset of the first stage down to the submicrovolt level. The AD608's limiter output provides a hard-limited signal output at 400 mV p-p. The voltage gain of the limiting amplifier to this output is more than 100 dB. Transition times are 11 ns and the phase is stable to within 3 at 10.7 MHz for signals from -75 dBm to +5 dBm. The AD608 is enabled by a CMOS logic-level voltage input, with a response time of 200 ns. When disabled, the standby power is reduced to 300 W within 400 ns. The AD608 is specified for the industrial temperature range of -25C to +85C for 2.7 V to 5.5 V supplies and -40C to +85C for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.
W typ
GENERAL DESCRIPTION
The AD608 provides both a low power, low distortion, low noise mixer and a complete, monolithic logarithmic/limiting amplifier using a "successive-detection" technique. It provides both a high speed RSSI (Received Signal Strength Indicator) output with 80 dB dynamic range and a hard-limited output. The RSSI output is from a two-pole post-demodulation lowpass filter and provides a loadable output voltage of +0.2 V to +1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply at a typical power level of 21 mW at 3 V.
FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN 3dB NOMINAL INSERTION LOSS IF INPUT -75dBm TO +15dBm2 7 BPF DRIVER VMID MID-SUPPLY IF BIAS LOHI BIAS VPS1 COM1 1 +2.7V TO 5.5V 2 3 LO INPUT -16dBm COM2 4 16 CMOS LOGIC INPUT NOTES:
1 2
110dB LIMITER GAIN 90dB RSSI 7 FULL-WAVE RECTIFIER CELLS IFHI 9 5-STAGE IF AMPLIFIER (16dB PER STAGE)
6mA MAX OUTPUT (890mV INTO 165) RFHI RF INPUT -95 TO -15dBm1 RFLO 6 LO PREAMP 5 MIXER
2MHz LPF
RSSI
RSSI OUTPUT 11 20mV/dB 0.2V TO 1.8V
MXOP
10.7MHz BANDPASS FILTER 330 330 10nF
COM3 12 VPS2 LMOP FINAL LIMITER 15 LIMITER OUTPUT 400mVp-p 14 +2.7V TO 5.5V
8 100nF 100
10 IFLO 13 18nF FDBK
AD608
50A
PRUP -15dBm = 56mV MAX FOR LINEAR OPERATION 39.76V RMS TO 397.6mV RMS FOR 1dB RSSI ACCURACY
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
(c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD608-SPECIFICATIONS (@ T = + 25 C, Supply = 3 V, dBm is referred to 50
A
, unless otherwise noted)
Min AD608 Typ Max 500 -16 24 11 16 -15 -5 1.9 3 110 -75 10 3 3 2 400 11 200 17.27 20 -85 0.2 1.8 1 200 250 1.5 75 200 400 100 2.7 4.5 7.3 -25 -40 +85 +85 5.5 5.5 23.27 Units MHz dBm dB dB dB dBm dBm k pF dB dBm k pF Degree V mV p-p ns mV/dB dBm V V V dB ns V A ns ns A V V mA C C
Model Conditions MIXER PERFORMANCE RF and LO Frequency Range LO Power Conversion Gain Noise Figure 1 dB Compression Point Third-Order Intercept Input Resistance Input Capacitance LIMITER PERFORMANCE Gain Limiting Threshold Input Resistance Input Capacitance Phase Variation DC Level Output Level Rise and Fall Times Output Impedance RSSI PERFORMANCE Nominal Slope Nominal Intercept Minimum RSSI Voltage Maximum RSSI Voltage RSSI Voltage Intercept Logarithmic Linearity Error RSSI Response Time Output Impedance POWER-DOWN INTERFACE Logical Threshold Input Current Power-Up Response Time Power-Down Response Time Power-Down Current POWER SUPPLY Operating Range Powered Up Current OPERATING TEMPERATURE TMIN to TMAX TMIN to TMAX
Specifications subject to change without notice.
Input Terminated in 50 Driving Doubly-Terminated 330 IF Filter, ZIF = 165 Matched Input, fRF = 100 MHz Matched Input, fRF = 240 MHz Input Terminated in 50 fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz fRF = 100 MHz (See Table I) fRF = 100 MHz (See Table I) Full Temperature and Supply Range 3 rms Phase Jitter at 10.7 MHz 280 kHz IF Bandwidth
19
28
-75 dBm to +5 dBm IF Input Signal at 10.7 MHz Center of Output Swing (VPOS-1) Limiter Output Driving 5 k Load Driving a 5 pF Load At 10.7 MHz At VPOS = 3 V; Proportional to VPOS -75 dBm Input Signal +5 dBm Input Signal 0 dBm Input Signal -75 dBm to +5 dBm Input Signal at IFHI 90% RF to 50% RSSI At Midscale System Active on Logical High For Logical High Active Limiter Output To 200 A Supply Current
1.57
1.82
-25C to +85C -40C to +85C VPOS = 3 V VPOS = 2.7 V to 5.5 V VPOS = 4.5 V to 5.5 V
-2-
REV. B
AD608
ABSOLUTE MAXIMUM RATINGS 1 PIN DESCRIPTIONS
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . . +6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Temperature Range . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 16-Pin SOIC Package: JA = 110C/W.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Mnemonic VPS1 COM1 LOHI COM2 RFHI RFLO MXOP VMID IFHI IFLO RSSI COM3 FDBK VPS2 LMOP PRUP
Description Positive Supply Input Common Local Oscillator Input Connection Common RF Input, Noninverting RF Input, Inverting Mixer Output Midpoint Supply Bias Output IF Input, Noninverting IF Input, Inverting Received Signal Strength Indicator Output Output Common Offset-Null Feedback Loop Output Limiter Positive Supply Input Limiter Output Power-Up
ORDERING GUIDE
Model AD608AR
Temperature Range -25C to +85C, 2.7 V to 5.5 V Supplies; -40C to +85C, 4.5 V to 5.5 V Supplies
Package Option R-16A*
*R = Small Outline IC (SOIC).
TERMINAL DIAGRAM
VPS1 COM1 LOHI COM2 RFHI RFLO MXOP VMID
1 2 3 4 5 6 7 8
16 PRUP 15 LMOP 14 VPS2
AD608
13 FDBK
TOP VIEW 12 COM3 (Not to Scale) 11 RSSI 10 IFLO 9 IFHI
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD608 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD608
PRUP IN U1A TRIGGER U1B 4.7k
VPOS 0.1F 1nF 1 VPS1 PRUP 16 LMOP 15 VPS2 14 FDBK 13 COM3 12 RSSI 11 IFLO 10 IFHI 9 100 NC 10nF 47k NC
47k 1 VPS1 VPOS 0.1F 0.1F 51.1 1nF 51.1 1nF 2 COM1 3 LOHI 4 COM2 5 RFHI 6 RFLO 7 MXOP 332 8 VMID IFHI 9 0.1F 301 332 0.1F IF INPUT 54.9
54.9
2 COM1 3 LOHI 1nF 4 COM2 5 RFHI
18nF 18nF
PRUP 16 LMOP 15 VPS2 14 FDBK 13 COM3 12 RSSI 11 IFLO 10 18nF 100 10nF RSSI OUTPUT 0.1F LMOP OUT
LO IN 51.1
RF IN 51.1 1nF
6 RFLO 7 MXOP 8 VMID 332 0.1F 301 IF OUT 0.1F
AD608
332
AD608
NC = NO CONNECT
U1 - 74HC00
Figure 1. IF Test Board Schematic
Figure 2. Mixer Test Board Schematic
25.0
0 -1
3.0
24.5 CONVERSION GAIN - dB
2.5
-2
24.0
RESPONSE - dB
2.0
-3
RSSI - V
5V 1.5
23.5
-4 -5 -6
23.0
1.0 3V 0.5
22.5
-7 -8
0 50 100 150 200 250 300 350 400 450 500 RF FREQUENCY - MHz
0 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER AT IFHI - dBm 10
22.0
0
10
20 30 40 50 60 IF FREQUENCY - MHz
70
80
Figure 3. Mixer Conversion Gain vs. Frequency
3.0 +85 +25 -25 2.0
Figure 4. Mixer IF Port Bandwidth
Figure 5. IF RSSI Output vs. Supply Voltage (Ambient Temperature)
4.0 3.0
2.5
FLUKE 6082A SYNTHESIZER
IF TEST BOARD
RSSI ERROR - dB
2.0 1.0 0 5V -1.0 -2.0 -3.0 -4.0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER - dBm 3V
RSSI - V
IFHI
1.5
RSSI VPOS
DMM HP34401A
10.7 MHz
1.0
DCPS HP3366A
3V
0.5
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER - dBm
0
10
Figure 6. IF RSSI Output vs. Temperature (3 V Supply)
Figure 7. Test Circuit for IF RSSI Output vs. Supply Voltage (Ambient Temperature) (Figure 5) and IF RSSI Output vs. Temperature (3 V Supply) (Figure 6) and RSSI Error vs. Input Power (Figure 8)
0
10
Figure 8. RSSI Error vs. Input Power
-4-
REV. B
AD608
800mV/DIV
RSSI
60mV/DIV
1V /DIV
PRUP
100ns/DIV
LMOP
100ns/DIV
20ns/DIV
Figure 9. RSSI Power-Up Response
FLUKE 6082A SYNTHESIZER HP54120A DIGITAL OSCILLOSCOPE CH 1
Figure 13. Limiter Rise and Fall Times
IF TEST BOARD IFHI RSSI TRIGGER
TEK P6201 FET PROBE
FLUKE 6082A SYNTHESIZER
IF TEST BOARD IFHI LMOP VPOS
10.7 MHz 0dBm
PRUP
CH 2
TEK P6201 FET PROBE
HP54120A DIGITAL OSCILLOSCOPE
VPOS
10.7 MHz 0dBm
DCPS HP3366A
3V
DCPS HP3366A
3V
Figure 10. Test Circuit for RSSI Power-Up Response (Figure 9)
200mV/DIV
Figure 14. Test Circuit for Limiter Rise and Fall Times (Figure 13)
220mV/DIV
LMOP
100ns/DIV
IFHI
1V/DIV
PRUP
RSSI
800mV/DIV
50ns/DIV
100ns/DIV
Figure 11. RSSI Pulse Response/RSSI Rise Time
FLUKE 6082A SYNTHESIZER COUPLER 10.7 MHz 0dBm DCPS HP3366A 3V HP54120A DIGITAL OSCILLOSCOPE MCL ZDC-20-1 CH 1 IF TEST BOARD IFHI VPOS RSSI TEK P6201 FET PROBE
Figure 15. Limiter Power-Up Response Time
FLUKE 6082A SYNTHESIZER IF TEST BOARD IFHI 10.7 MHz 0dBm PRUP LMOP TRIGGER HP54120A DIGITAL OSCILLOSCOPE CH 1 CH 2
TEK P6201 FET PROBE
CH 2
VPOS
DCPS HP6633A
3V
Figure 12. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 11)
Figure 16. Test Circuit for Limiter Power-Up Response Time (Figure 15)
REV. B
-5-
AD608
5 4
10 9
RELATIVE PHASE - Degrees
3 2 1 0 -1 -2 -3 -4 -5 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER - dBm 0 10
RMS JITTER - Degrees
8 7 6 5 4 3 2 1 0 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER AT IFHI - dBm 10
Figure 17. Limiter Phase Performance vs. Input Power at IFHI
Figure 19. Limiter Jitter Performance vs. Input Power at IFHI
MCL FLUKE 6082A SYNTHESIZER ZDC-20-1 COUPLER 10.7 MHz
IF TEST BOARD TEK P6201 IFHI RSSI FET PROBE HP8447A DCPS HP3366A 3V BPF 280kHz BW 10.7MHz CF TRIG TOKO SK107MK1-A0-10 HP54120A DIGITAL OSCILLOSCOPE CH 1
HP8494A HP8495A
Figure 18. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI (Figure 17) and Limiter Jitter Performance vs. Input Power at IFHI (Figure 19)
-6-
REV. B
AD608
THEORY OF OPERATION Mixer Gain
The AD608 (Figure 20) consists of a mixer followed by a logarithmic IF strip with RSSI and hard limited outputs. Each section will be described below.
Mixer
The mixer is a doubly-balanced modified Gilbert cell mixer. Its maximum input level for linear operation is 56.2 mV regardless of the impedance across the mixer's inputs, or -15 dBm for a 50 input termination. The input impedance of the mixer can be modeled as a simple parallel RC network; the values versus frequency are listed in Table I. The bandwidth from the RF input to the IF output at MXOP pin is -1 dB at 30 MHz and then falls off rapidly (Figure 4).
24dB MIXER GAIN 3dB NOMINAL INSERTION LOSS IF INPUT -75dBm TO +15dBm 2. IFHI 10.7MHz BANDPASS 9 FILTER 330 8 100nF 330 10nF 10 100 13 18nF
The mixer's conversion gain is the product of its transconductance and the impedance seen at pin MXOP. For a 330 parallel-terminated filter at 10.7 MHz, the load impedance is 165 , the gain is 24 dB, and the output is 15.85 x 56.2 mV, or 891 mV, centered on the midpoint of the supply voltage. For other load impedances, the expression for the gain in dB is
GdB = 20 log10 (0.0961 RL )
The mixer's gain can be increased or decreased by changing RL, the load impedance at pin MXOP. The limitations on the mixer's gain are the 6 mA maximum output current at MXOP and the maximum allowable voltage swing at pin MXOP, which is 1.0 V for a 3 V supply or 5 V supply.
110dB LIMITER GAIN 90dB RSSI 7 FULL-WAVE RECTIFIER CELLS
RFHI RF INPUT -95 TO -15dBm 1.
5
6mA MAX OUTPUT (890mV INTO 165) MIXER
RSSI OUTPUT 11 20mV/dB 0.2V TO 1.8V COM3 12 RSSI VPS2 14 +2.7V TO 5.5V 15 LIMITER OUTPUT 400mVp-p
MXOP BPF DRIVER VMID
7
RFLO 6 LO PREAMP
5-STAGE IF AMPLIFIER (16dB PER STAGE)
LMOP FINAL LIMITER
MID-SUPPLY IF BIAS LOIP BIAS VPS1 COM1 1 2 3 LO INPUT -16dBm COM2 4 16 CMOS LOGIC INPUT PRUP
IFLO
FDBK
AD608
50 A
+2.7V TO 5.5V
NOTES:
1. -15dBm = 56mV MAX FOR LINEAR OPERATION 2. 39.76mV RMS TO 396.6mV RMS FOR 1 dB RSSI ACCURACY
Figure 20. Functional Block Diagram
Table I. Mixer Input Impedance vs. Frequency
Frequency (MHz) 45 70 100 200 300 400 500
Resistance (Ohms) 2800 2600 1800 1200 760 520 330
Capacitance (pF) 3.1 3.1 3.1 3.1 3.2 3.4 3.6
REV. B
-7-
AD608
IF Filter Terminations
The AD608 was designed to drive a parallel-terminated 10.7 MHz bandpass filter with a 330 impedance. With a 330 parallelterminated filter, pin MXOP sees a 165 termination and the gain is nominally 24 dB. Other filter impedances and gains can be accommodated by either accepting an increase or decrease in gain in proportion to the filter impedance or by keeping the impedance seen by MXOP a nominal 165 (by using resistive dividers or matching networks). Figure 21 shows a simple resistive voltage divider for matching an assortment of filter impedances, and Table II lists component values.
The Logarithmic IF Amplifier
5 k load. In the absence of an input signal, the limiter's output will limit on noise fluctuations, which produces an output that continues to swing 400 mV p-p but with random zero crossings.
Offset Feedback Loop
The logarithmic IF amplifier consists of five amplifier stages of 16 dB gain each, plus a final limiter. The IF bandwidth is 30 MHz (-1 dB) and the limiting gain is 110 dB. The phase skew is 3 from -75 dBm to +5 dBm (approximately 111 V p-p to 1.1 V p-p). The limiter output impedance is 200 and the limiter's output drive is 200 mV (400 mV p-p) into a
24dB MIXER GAIN 12dB NOMINAL INSERTION LOSS (ASSUMES 6dB IN FILTER) BANDPASS FILTER MIXER
Because the logarithmic amplifier is dc coupled and has more than 110 dB of gain from the input to the limiter output, a dc offset at its input of even a few V would cause the output to saturate. Thus, the AD608 uses a low frequency feedback loop to null out the input offset. Referring to Figure 21, the loop consists of a current source driven by the limiter, which sends 50 A current pulses to pin FDBK. The pulses are low pass filtered by a -network consisting of C1, R4, and C5. The smoothed dc voltage that results is subtracted from the input to the IF amplifier at pin IFLO. Because this is a high gain amplifier with a feedback loop, care should be taken in layout and component values to prevent oscillation. Recommended values for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table II.
110dB LIMITER GAIN 90dB RSSI 7 FULL-WAVE RECTIFIER CELLS IFHI 9
2MHz LPF
11 RSSI 12 COM3 14 VPS2
RFHI 5
MXOP BPF DRIVER VMID
R2 7 R1 8 100nF R4 13 C1 R3 C5 10
RFLO 6 LO PREAMP
5-STAGE IF AMPLIFIER (16dB PER STAGE) FINAL LIMITER
15 LMOP
MID-SUPPLY IF BIAS LOHI BIAS VPS1 COM1 1 +5V C1 1F C2 100pF LO INPUT -16dBm 2 3 COM2 4 16 47k CMOS LOGIC INPUT PRUP
IFLO
FDBK
AD608
50A
Figure 21. Applications Diagram for Common IFs and Filter Impedances
Table II. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
IF 450 kHz2 455 kHz 6.5 MHz 10.7 MHz
Filter Impedance 1500 1500 1000 330
Filter Termination Resistor Values1 for 24 dB of Mixer Gain R1 174 174 178 330 R2 1330 1330 825 0 R3 1500 1500 1000 330
Offset Null Feedback Loop Values R4 1000 1000 100 100 C1 200 nF 200 nF 18 nF 18 nF C5 100 nF 100 nF 10 nF 10 nF
NOTES 1 Resistor values were calculated so that R1 + R2 = Z FILTER and R1 (R2+ZFILTER) = 165 . 2 Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz).
-8-
REV. B
AD608
RSSI Output Power Consumption
The logarithmic amplifier uses a successive detection architecture. Each of the five stages has a full-wave detector; two additional high level detectors are driven through attenuators at the input to the limiting amplifiers, for a total of seven detector stages. Because each detector is a full-wave rectifier, the ripple component in the resulting dc is at twice the IF. The AD608's low-pass filter has a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz ripple that results from a 10.7 MHz IF. For operation at lower IFs such as 450 kHz or 455 kHz, the AD608 requires an external low-pass filter with a single pole located at 90 kHz, a decade below the 900 kHz ripple frequency for these IFs. The RSSI range is from the noise level at approximately -80 dBm to overload at +15 dBm and is specified for 1 dB accuracy from -75 dBm to +5 dBm. The +15 dBm maximum IF input is provided to accommodate bandpass filters of lower insertion loss than the nominal 4 dB for 10.7 MHz ceramic filters.
Digitizing the RSSI
The total power-supply current of the AD608 is a nominal 7.3 mA. The power is signal-dependent, partly as the RSSI output increases (the current is increased by 200 A at an RSSI output of +1.8 V) but mostly due to the IF BPF consumption when being driven to 891 mV assuming a 4 dB loss in this filter and a peak input of +5 dBm to the log-IF amp, and temperature dependent, as the biasing system used in the AD608 is proportional to absolute temperature (PTAT).
Troubleshooting
The most common causes of problems with the AD608 are incorrect component values for the offset feedback loop, poor board layout, and pickup of RFI, which all cause the AD608 to "lose" the low end (typically below -65 dBm) of its RSSI output and cause the limiter to swing randomly. Both poor board layout and incorrect component values in the offset feedback loop can cause low level oscillations. Pickup of RFI can be caused by improper layout and shielding of the circuit.
In typical cellular radio applications, the RSSI output of the AD608 will be digitized by an A/D converter. The AD608's RSSI output is proportional to the power-supply voltage, which not only allows the A/D converter to use the supply as a reference but also causes the RSSI output and the A/D converter's output to track over power supply variations, reducing system errors and component costs.
REV. B
-9-
AD608
Applications
Figure 22 shows the AD608 configured for operation in a digital system at a 10.7 MHz IF. The filter's input and output impedance are parallel terminated using 330 resistors and the conversion gain is 24 dB. The RF port is terminated in 50 ; in a typical application the input would be matched to a SAW filter using the impedance data shown previously in Table I.
Figure 23 shows the AD608 configured for narrowband FM operation at a 450 kHz or 455 kHz with an external discriminator. The IF filter has 1500 input and output impedances-- the input is matched via a resistive divider and the output is terminated in 1500 . The discriminator requires 1 V p-p drive from a 1 k source impedance, here provided by a gain-of-2.5 Class A amplifier.
VPOS C1 1F 1 VPS1 LO INPUT -16dBm R5 51.1 C2 100pF 2 COM1 3 LOHI 4 COM2 5 RFHI RF INPUT -95dBm TO -15dBm C3 100pF R6 51.1 C4 100pF 6 RFLO 7 MXOP 8 VMID PRUP 16 LMOP 15 VPS2 14 FDBK 13 COM3 12 RSSI 11 IFLO 10 IFHI 9 C6 10nF RSSI OUTPUT +0.2V TO +1.8V (20mV/dB) C7 18nF R4 47k LIMO POWER-UP 3V CMOS LIMITER OUTPUT VPOS -1V 200mV SUPPLY 2.7V TO 5.5V
R3 100
AD608
BIAS POINT AT VPOS/2
10.7MHz BPF Z = 330
R1 330 C5 0.1F
R2 330
OFFSET-CONTROL LOOP FILTER
BPF REVERSE TERMINATION IF BIAS POINT DECOUPLING
BPF TERMINATION
Figure 22. Application at 10.7 MHz. The Bandpass Filter Can Be a Toko Type SK107 or Murata Type SFE10.7
JUMPER PRUP R16 47k C5 0.1F C8 0.1F
+5V GND C1 0.1F LOHI R1 51.1 C2 1nF
1 VPS1 2 COM1 3 LOHI 4 COM2
PRUP 16 LMOP 15 VPS2 14 FDBK 13 COM3 12 RSSI 11 IFLO 10 IFHI 9
R14 8.66k R15 24.9k
R13 402
C11 Q1 0.1F
F2 CR1 CR2 R8 1k R9 1k
R10 3.3k AUDIO
R12 1k
RFHI R2 51.1 C3 1nF C4 1nF R7 1130 R3 374
5 RFHI 6 RFLO 7 MXOP 8 VMID F1
R6 1k
C9 0.2F
R5 200 RSSI
C10 0.01F
R11 3.3k
C6 0.1F
AD608
R4 1.5k
F1: TOKO HCFM2-455B F2: MURATA CFY455S CR1, CR2: 1N60 Q1: 2N3906 C7 0.1F
Figure 23. Narrowband FM Application at 450 kHz or 455 kHz
-10-
REV. B
AD608
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC (R-16A)
16
9 0.1574 (4.00) 0.1497 (3.80)
PIN 1 1 8
0.2440 (6.20) 0.2284 (5.80)
0.3937 (10.00) 0.3859 (9.80) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0
0.0196 (0.50) 0.0099 (0.25)
x 45
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
REV. B
-11-
AD608
-12-
C1990b-2-7/96
REV. B
PRINTED IN U.S.A.

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